ASIC Design Engineer

<img src="https://we-work-remotely.imgix.net/logos/0171/6098/logo.gif?ixlib=rails-4.0.0&w=50&h=50&dpr=2&fit=fill&auto=compress" /> <p> <strong>Headquarters:</strong> San Jose, Costa Rica <br /><strong>URL:</strong> <a href="http://cornelis.com">http://cornelis.com</a> </p> <p>At Cornelis we’re building the future of AI and HPC networking with an AI-first approach to silicon and software development. We’re seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.<br></p> <p><br></p> <p><span><span>Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions.  </span><br></span></p> <p><br></p> <p><span><span>We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles.  </span><br></span></p> <p><br></p> <p><span><span>Cornelis Networks is hiring talented ASIC Design Engineers with deep experience in one or more of the key areas required to build the world-class SoCs to be deployed in high performance computing, high performance data analytics, and artificial intelligence interconnect solutions.</span><br></span></p> <p><br></p> <p><span><span><span>Key Responsibilities</span></span><br></span></p> <ul> <li><span><span>Implementation of the advanced ethernet protocols for the next generation ethernet ASICs.  </span><br></span></li> </ul> <ul> <li><span><span>Write micro architecture specifications. </span><br></span></li> </ul> <ul> <li><span><span>Pre-silicon: Define timing constraints for the RTL block and work with Physical Design engineers for timing optimization.</span><br></span></li> </ul> <ul> <li><span><span>Pre-silicon: Work with the verification engineers to create block/system level test plans and ensure that the design is adequately covered.</span><br></span></li> </ul> <ul> <li><span><span>Post-silicon: Work with hardware/firmware/software engineers to resolve ASIC issues.  </span><br></span></li> </ul> <p><span><br></span></p> <p><span><span><span>Minimum Qualifications</span></span><br></span></p> <ul> <li><span><span>B.S. or M.S.  degree in Computer or Electrical Engineering. </span><br></span></li> </ul> <ul> <li><span><span>3 + years of post-college experience in digital design with proficiency in Verilog, System Verilog.</span><br></span></li> </ul> <ul> <li><span><span>Relevant experience in timing closure and familiarity with modern physical design methodologies.</span><br></span></li> </ul> <ul> <li><span><span>Demonstrated strength with system level debug and determining root cause of technical issues.</span><br></span></li> </ul> <ul> <li><span><span>Strong verbal and written communications skills.</span></span></li> </ul> <p><br><br></p> <p><span><span><span>Preferred Qualifications</span></span><br></span></p> <ul> <li><span><span>Experience with Ethernet architecture and Networking protocols. </span><br></span></li> <li><span><span>Familiarity and experience in design of some ethernet protocols applicable to ethernet adapters and switches.</span><br></span></li> <li><span>Experience with multiple clock designs and asynchronous interfaces</span></li> </ul> <p><span><br></span></p> <p><span><span>Job Location:<span> </span></span>This role may work remote from Costa Rica via an EOR (Employer of Record).</span></p> <p><br></p> <p>We offer a competitive compensation package that includes base salary, performance incentives and equity participation.</p> <p><br></p> <p>At Cornelis Networks, your compensation is only one component of your comprehensive total rewards package. Comp